An environment for the automatic verification of digital circuits

Finalista del Premi Cercle Fiber al millor Projecte Final de Carrera (curs 2010-2011)English: The aim of this project is to implement a system for the automatic verification of digital circuits written in a high-level hardware description language (Verilog), to be potentially used to assist a electronic design automation course

Structure discovery techniques for circuit design and process model visualization

Graphs are one of the most used abstractions in many knowledge fields because of the easy and flexibility by which graphs can represent relationships between objects. The pervasiveness of graphs in many disciplines means that huge amounts of data are available in graph form, allowing many opportunities for the extraction of useful structure from these graphs in order to produce insight into the data. In this thesis we introduce a series of techniques to resolve well-known challenges in the areas of digital circuit design and process mining. The underlying idea that ties all the approaches together is discovering structures in graphs. We show how many problems of practical importance in these areas can be solved utilizing both common and novel structure mining approaches. In the area of digital circuit design, this thesis proposes automatically discovering frequent, repetitive structures in a circuit netlist in order to improve the quality of physical planning. These structures can be used during floorplanning to produce regular designs, which are known to be highly efficient and economical. At the same time, detecting these repeating structures can exponentially reduce the total design time. The second focus of this thesis is in the area of the visualization of process models. Process mining is a recent area of research which centers on studying the behavior of real-life systems and their interactions with the environment. Complicated process models, however, hamper this goal. By discovering the important structures in these models, we propose a series of methods that can derive visualization-friendly process models with minimal loss in accuracy. In addition, and combining the areas of circuit design and process mining, this thesis opens the area of specification mining in asynchronous circuits. Instead of the usual design flow, which involves synthesizing circuits from specifications, our proposal discovers specifications from implemented circuits. This area allows for many opportunities for verification and re-synthesis of asynchronous circuits. The proposed methods have been tested using real-life benchmarks, and the quality of the results compared to the state-of-the-art.Els grafs són una de les representacions abstractes més comuns en molts camps de recerca, gràcies a la facilitat i flexibilitat amb la que poden representar relacions entre objectes. Aquesta popularitat fa que una gran quantitat de dades es puguin trobar en forma de graf, i obre moltes oportunitats per a extreure estructures d'aquest grafs, útils per tal de donar una intuïció millor de les dades subjacents. En aquesta tesi introduïm una sèrie de tècniques per resoldre reptes habitualment trobats en les àrees de disseny de circuits digitals i mineria de processos industrials. La idea comú sota tots els mètodes proposats es descobrir automàticament estructures en grafs. En la tesi es mostra que molts problemes trobats a la pràctica en aquestes àrees poden ser resolts utilitzant nous mètodes de descobriment d'estructures. En l'àrea de disseny de circuits, proposem descobrir, automàticament, estructures freqüents i repetitives en les definicions del circuit per tal de millorar la qualitat de les etapes posteriors de planificació física. Les estructures descobertes poden fer-se servir durant la planificació per produir dissenys regulars, que son molt més econòmics d'implementar. Al mateix temps, la descoberta i ús d'aquestes estructures pot reduir exponencialment el temps total de disseny. El segon punt focal d'aquesta tesi és en l'àrea de la visualització de models de processos industrials. La mineria de processos industrials es un tema jove de recerca que es centra en estudiar el comportament de sistemes reals i les interaccions d'aquests sistemes amb l'entorn. No obstant, quan d'aquest anàlisi s'obtenen models massa complexos visualment, l'estudi n'és problemàtic. Proposem una sèrie de mètodes que, gràcies al descobriment automàtic de les estructures més importants, poden generar models molt més fàcils de visualitzar que encara descriuen el comportament del sistema amb gran precisió. Combinant les àrees de disseny de circuits i mineria de processos, aquesta tesi també obre un nou tema de recerca: la mineria d'especificacions per circuits asíncrons. En l'estil de disseny asíncron habitual, sintetitzadors automàtics generen circuits a partir de les especificacions. En aquesta tesi proposem el pas invers: descobrir automàticament les especificacions de circuits ja implementats. Així, creem noves oportunitats per a la verificació i la re-síntesi de circuits asíncrons. Els mètodes proposats en aquesta tesi s'han validat fent servir dades obtingudes d'aplicacions pràctiques, i en comparem els resultats amb els mètodes existents

A hierarchical approach for generating regular floorplans

© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksThe complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more reusable parts. In this work we introduce HiReg, a new floorplanning algorithm that generates regular floorplans. HiReg automatically extracts repeating patterns in a design by using graph mining techniques. Regularity is exploited by reusing the same floorplan for multiple instances of a pattern, as long as neither area, wire length or existing hierarchy constraints are violated or compromised. The proposed scheme is targeted towards early system-level design of chip multiprocessors (CMPs). Experiments show the scalability of the method for many-core CMPs and competitive results in area and wire lengthPeer ReviewedPostprint (author's final draft

La expresión de proinsulina atenúa los trastornos de la retina asociados a la edad en distintos modelos de envejecimiento fisiopatológico

Póster presentado en el XXXVI Congreso de la Sociedad Española de Bioquímica y Biología Molecular SEBBM, celebrada del 3 al 6 de septiembre de 2013 en Madrid (España)Peer Reviewe

Jutge.org: characteristics and experiences

Jutge.org is an open educational online programming judge designed for students and instructors, featuring a repository of problems that is well organized by courses, topics and difficulty. Internally, Jutge.org uses a secure and efficient architecture and integrates modern verification techniques, formal methods, static code analysis and data mining. Jutge.org has exhaustively been used during the last decade at the Universitat Politecnica de Catalunya to strengthen the learn-by-doing approach in several courses. This paper presents the main characteristics of Jutge.org and shows its use and impact in a wide range of courses covering basic programming, data structures, algorithms, artificial intelligence, functional programming and circuit design.Peer ReviewedPostprint (author's final draft

Stroma-Mediated Resistance to S63845 and Venetoclax through MCL-1 and BCL-2 Expression Changes Induced by miR-193b-3p and miR-21-5p Dysregulation in Multiple Myeloma.

BH3-mimetics targeting anti-apoptotic proteins such as MCL-1 (S63845) or BCL-2 (venetoclax) are currently being evaluated as effective therapies for the treatment of multiple myeloma (MM). Interleukin 6, produced by mesenchymal stromal cells (MSCs), has been shown to modify the expression of anti-apoptotic proteins and their interaction with the pro-apoptotic BIM protein in MM cells. In this study, we assess the efficacy of S63845 and venetoclax in MM cells in direct co-culture with MSCs derived from MM patients (pMSCs) to identify additional mechanisms involved in the stroma-induced resistance to these agents. MicroRNAs miR-193b-3p and miR-21-5p emerged among the top deregulated miRNAs in myeloma cells when directly co-cultured with pMSCs, and we show their contribution to changes in MCL-1 and BCL-2 protein expression and in the activity of S63845 and venetoclax. Additionally, direct contact with pMSCs under S63845 and/or venetoclax treatment modifies myeloma cell dependence on different BCL-2 family anti-apoptotic proteins in relation to BIM, making myeloma cells more dependent on the non-targeted anti-apoptotic protein or BCL-XL. Finally, we show a potent effect of the combination of S63845 and venetoclax even in the presence of pMSCs, which supports this combinatorial approach for the treatment of MM

Del color de los ojos al interior del genoma. Nuevas tecnologías aplicadas a la educación: una experiencia en la enseñanza de la Genética

Depto. de Genética, Fisiología y MicrobiologíaFac. de Ciencias BiológicasFALSEsubmitte